As integrated circuit devices have become smaller, it is increasingly important to ensure that functional and reliable connections between integrated circuit devices and conductor elements within the integrated circuits can be readily and efficiently achieved and manufactured. Within integrated circuits of Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), connections are often made through the use of polycide gate electrodes. Commonly, the polycide gate electrode is a tungsten silicide polycide gate electrode formed of a tungsten silicide upper layer and a polysilicon lower layer which in turn resides upon a MOSFET gate oxide layer.
Although tungsten silicide polycide gate electrodes within MOSFETs provide good surfaces onto which contact with conductor elements can be established, these types of arrangements tend to suffer from various drawbacks. For example, tungsten silicide polycide gate electrodes suffer from problems such as excess fluorine migration. This fluorine originates from tungsten hexafluoride, which is one of the materials used in chemical vapor deposition (CVD) of the tungsten silicide layer, and tends to occur between the tungsten silicide layer and the polysilicon layer/oxide layer interface therebelow, under high temperature annealing. This results in the thickness of the gate oxide layer having to be increased.
A further problem which is encountered with this particular type of arrangement resides in that dopants from within the polysilicon layer tend to redistribute during the thermal processing of the tungsten silicide polycide gate electrode. A yet further problem resides in that the tungsten silicide layers exhibit a high resistivity when formed upon large grain polysilicon layers.
In connection with the above mentioned problems, a method of forming a gate electrode for multiple polysilicon layer has been disclosed in U.S. Pat. No. 5,350,698 issued to Huang et al. This reference discloses the formation of multiple amorphous silicon layers which are subsequently annealed to form polysilicon layers, along with intervening silicon oxide layers and an optional terminal tungsten silicide layer. This arrangement is directed to limiting the channeling of ion implants observed through single polysilicon layers of equivalent thickness. Multiple amorphous silicon layers are discloses as being preferred since, upon annealing, they form a larger grain size than encountered with equivalent types of multiple polysilicon layer structures.
Another technique proposed in connection with these drawbacks resides in a method wherein multiple polysilicon layers or multiple amorphous silicon layers are interdispersed with silicon oxide layers. It has been further proposed to use stacked amorphous silicon (SAS) multilayer structures without interdispersed silicon oxide layers. This latter type of stacked amorphous silicon (SAS) multilayer structure, when annealed to form the polysilicon layers, is said to improve the performance of the resulting integrated circuit device. More specifically, the use of stacked amorphous silicon (SAS) multiple layer structures has been reported to, following annealing, suppress boron penetration from polysilicon gate electrodes into underlying thin gate oxide layers within P-metal oxide semiconductor field effect transistors (pMOSFETs).
Further efforts in connection with developing MOSFETs with tungsten silicide polycide gate electrodes exhibiting good diffusion barrier properties, good dopant retention properties, and good contact resistance properties, is disclosed in U.S. Pat. No. 5,710,454 issued to Wu on Jan. 20, 1998. Wu discloses a method of forming tungsten silicide polycide gate electrodes within MOSFET which is directed to limiting redistribution of dopants from within the polysilicon layer of the tungsten silicide polycide gate electrode.
In accordance with Wu's technique, a semiconductor substrate gate oxide layer is firstly formed. A first polysilicon layer is then formed on the gate oxide layer by initially forming an amorphous silicon layer and then annealing to convert it to polysilicon. A second polysilicon layer is formed through a similar process. That is to say, amorphous silicon is formed and then converted to polysilicon through annealing. The tungsten silicide layer is then formed on the second polysilicon layer through the use of chemical vapor deposition (CVD). With this method, the first and second polysilicon layers have a crystallite size no greater than 0.3 microns, and have a dopant concentration of greater than 1E16 atoms cm.sup.3.
While this method purports to inhibit the diffusion of fluorine from the tungsten silicide layer through the thermal annealing of a stacked amorphous silicon (SAS) multilayer structure, it has nevertheless tended to suffer from the drawback that the tungsten silicide layer tends to separate, that is to say undergo lifting, from the underlying polysilicon layers, with the result that productivity is accordingly reduced.
Accordingly, there exists a need for a stacked gate structure which exhibits both resistance to layer separation and dopant diffusion.